Renesas Electronics: Sr Staff /Staff Engineer, RTL Design — Noida, India

Renesas Electronics lists a Sr Staff /Staff Engineer, RTL Design opening in Noida, India. The position is listed as full-time. The job description covers AI.

Recruitment overview

OrganisationRenesas Electronics
Post / roleSr Staff /Staff Engineer, RTL Design
Employment typeFull-time
Notification / job ID20031158_2026-07-15
Job locationNoida, India
Work arrangementOn-site
Educational qualificationDegree / qualification: MTech/BTech in EE/CS with hardware engineering experience of 10+ years
Experience requiredMTech/BTech in EE/CS with hardware engineering experience of 10+ years
Salary / stipendSee employer notice for pay details
Last date to applySee official notice

About Renesas Electronics

Renesas Electronics develops semiconductors for automotive, industrial, infrastructure and connected-device applications. Its employer description identifies microcontrollers, system-on-chip devices, analogue components and power products within its portfolio. These components form part of electronic systems made by other manufacturers. Renesas also describes combining complementary products into solutions for customers, connecting individual chips with the needs of an end application. Its business therefore involves both semiconductor technology and how that technology is used in wider electronic products.

The position and its setting

Renesas Electronics lists Sr Staff /Staff Engineer, RTL Design in Noida, India, under reference 20031158_2026-07-15. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

  • Employment type: Full-time
  • Employer listing date: 17 July 2026
  • Brands: Renesas Electronics

Responsibilities and work described

  • Collaboration: with system architects and micro-architects to define high-level, implementable SoC specifications
  • Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets
  • Influence SoC definition, features, and adopt physical design friendly partitioning
  • Leadership: RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains
  • Demonstrate proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA)
  • Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects
  • Design: and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4
  • Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery
  • Support: post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams
  • Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle
  • Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects
  • Delivery: overall leadership and tracking of the team’s goals
  • Contribution: to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc

Essential requirements and candidate background

  • MTech/BTech in EE/CS with hardware engineering experience of 10+ years
  • Experience: micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA
  • Experience: development of SERDES PCS/PMA logic including scrambling/descrambling, data encoding/decoding, block synchronization etc
  • Understanding: electrical characteristics and signoff needed for meeting PCIe/UCIe standards compliance
  • Able to work with teams across the globe and possess good communication skills

Experience and professional background

  • Experience: high-speed interface design and hands on knowledge of Industry standard High speed protocols like PCIe4/PCIe6/UCIe etc. is desirable

Preferred experience and additional strengths

  • Experience: post-silicon bring-up and debug is a plus

Location, schedule and contract conditions

  • Work arrangement: On-site
  • Advertised location: Noida, India

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Sr Staff /Staff Engineer, RTL Design vacancy is not an offer for reference 20031158_2026-07-15; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Renesas Electronics

Applications follow the official employer page linked below.

Open the official Renesas Electronics posting below and match the title and reference 20031158_2026-07-15.

Compare your qualifications and experience with the essential conditions for the Noida, India position, then read the preferred criteria separately.

Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.

Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.

Practical preparation: AI

An AI-related example should make the task and evaluation explicit. Explain the inputs, the system’s intended output and how you checked errors, usefulness or reliability, rather than relying on the model name alone.

Relevant skills

  • AI/ML
  • AI
  • compliance
  • communication

Important links

Official notification / job descriptionOpen official page
Online application portalOpen official page

Read the complete official notice before applying. Availability and requirements can change.

For corrections, see our editorial policy and contact information.