Renesas Electronics: Staff Engineer, Physical Design — Bengaluru, KA, India
Renesas Electronics lists a Staff Engineer, Physical Design opening in Bengaluru, KA, India. The position is listed as full-time. The job description covers Python, electrical engineering.
Recruitment overview
| Organisation | Renesas Electronics |
|---|---|
| Post / role | Staff Engineer, Physical Design |
| Employment type | Full-time |
| Notification / job ID | 20025458_2026-02-17 |
| Job location | Bengaluru, KA, India |
| Work arrangement | Hybrid |
| Educational qualification | Degree / qualification: Education:M.Tech/ B.Tech in Electrical Engineering |
| Experience required | 7+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below) |
| Salary / stipend | See employer notice for pay details |
| Last date to apply | See official notice |
About Renesas Electronics
Renesas Electronics develops semiconductors for automotive, industrial, infrastructure and connected-device applications. Its employer description identifies microcontrollers, system-on-chip devices, analogue components and power products within its portfolio. These components form part of electronic systems made by other manufacturers. Renesas also describes combining complementary products into solutions for customers, connecting individual chips with the needs of an end application. Its business therefore involves both semiconductor technology and how that technology is used in wider electronic products.
The position and its setting
Renesas Electronics lists Staff Engineer, Physical Design in Bengaluru, KA, India, under reference 20025458_2026-02-17. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.
- Employment type: Full-time
- Employer listing date: 16 July 2026
- Brands: Renesas Electronics
Responsibilities and work described
- Leadership: MCU/subsystem/block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation
- Collaboration: closely with SoC-level teams to align on clocking and floor planning strategies, leveraging understanding of SoC methodologies without direct ownership of SoC-level activities
- Work: on the different power domains and implement UPF
- Apply knowledge of clocking methodologies to ensure subsystem clock domain integration aligns with overall SoC clock architecture
- Development: and refine subsystem closure methodologies and automation flows to improve design quality and efficiency
- Mentor and guide physical design engineers within the subsystem teams, promoting best practices and methodology adoption
- Work: cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration and closure
- Proactively identify and mitigate physical design risks, coordinating with SoC teams on potential impacts and solutions
Essential requirements and candidate background
- Education:M
- Tech/ B
- Tech in Electrical Engineering
- 7+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below)
- Expertise in timing closure, congestion management, and physical implementation at the block and subsystem level
- Understanding: SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them
- Experience: industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms
- Proficiency: scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development
- Deep knowledge of SoC design flows with ability to work closely with timing closure, power integrity, clocking, verification
- Understanding: low-power design techniques and power-aware physical implementation
Location, schedule and contract conditions
- Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day
- Work arrangement: Hybrid
- Advertised location: Bengaluru, KA, India
Pay and application dates
A verified salary figure is not established in this article. An online estimate for another Staff Engineer, Physical Design vacancy is not an offer for reference 20025458_2026-02-17; use the employer’s own pay disclosure and recruitment communication.
A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.
How to apply to Renesas Electronics
Applications follow the official employer page linked below.
Open the official Renesas Electronics posting below and match the title and reference 20025458_2026-02-17.
Compare your qualifications and experience with the essential conditions for the Bengaluru, KA, India position, then read the preferred criteria separately.
Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.
Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.
Practical preparation: Python
Python work is easier to assess through a concrete example than a list of libraries. Explain the problem, the input data, the parts you implemented and how you checked the output. Include a repository or a short technical note when you can share it.
Relevant skills
- Python
- electrical engineering
Important links
| Official notification / job description | Open official page |
|---|---|
| Online application portal | Open official page |
Read the complete official notice before applying. Availability and requirements can change.
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