Western Digital: Principal RFIC Design Engineer — San Jose, CA, United States

About Western Digital

Western Digital develops and manufactures data-storage technology for data centres, cloud platforms and enterprise infrastructure. Its employer introduction connects this work with the need to retain, manage and access information generated by digital systems and AI applications. The business brings engineering and manufacturing together around the physical systems behind data storage. Its described purpose is to make growing volumes of information available over time, supporting the infrastructure on which other digital services depend.

The position and its setting

Western Digital lists Principal RFIC Design Engineer in San Jose, CA, United States, under reference REF33119K. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

• Employment type: Full-time
• Employer listing date: 14 October 2026
• Business Function: ASIC Development
• Brands: Western Digital
• Work Location: San Jose Great Oaks Headquarters

Responsibilities and work described

• ESSENTIAL DUTIES AND RESPONSIBILITIES:
• Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks
• Job responsibilities require ability to communicate at all levels and with cross functional groups
• Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation, must be a team player, be adaptable, and accept constructive criticism

Essential requirements and candidate background

• Must have hands-on design and development experience in analog and mixed-signal integrated circuit
• Must have experience in at least one preferably multiple area of full CMOS circuit design and development in:
• Amplifiers – operational, instrumentation, wide-bandwidth etc
• PMIC – Linear and switched regulators, Low-drop out regulators etc
• Data converters – ADC, DAC, Flash and SAR type
• Must have experience in 40nm and below CMOS technology
• Must have a demonstrable track record of successful design releases and mass production
• Must have thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.)
• Experience: analog layout techniques of mismatch reduction, gradient suppression, parasitic effects minimization
• Experience: floor planning, block level routing and top level chip routing
• Knowledge: high performance and deep CMOS analog reliability considerations such as EM-IR, SOA and VDR and relevant mitigation techniques
• Functional knowledge of logic digital circuits and understanding of basic digital design flow
• Experience working with distributed design teams a plus
• Must possess written and verbal communication skills
• BSEE with minimum 10+ years of experience
• MSEE with minimum 8+ years of experience
• PhD with minimum 4+ years of experience

Location, schedule and contract conditions

For this overseas or regional listing, confirm work authorisation and any location restrictions with the employer. The location does not establish visa sponsorship or permission to work remotely from India.

• Work arrangement: On-site
• Advertised location: San Jose, CA, United States

Benefits mentioned by the employer

• The salary range is what we believe to be the range of possible compensation for this role at the time of this posting
• This range may be modified in the future
• If your position is non-exempt, you are eligible for overtime pay pursuant to company policy and applicable laws
• You may also be eligible for shift differential pay, depending on the shift to which you are assigned
• You may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan
• Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan
• RSU awards are also available to eligible new hires, subject to WD's Standard Terms and Conditions for Restricted Stock Unit Awards
• Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable
• Notice To Candidates: Please be aware that WD and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment
• Should you encounter any such requests, please report it immediately to WD Ethics Helpline or email compliance@wdc.com

Conditions requiring the complete notice

Some passages contain complex or combined conditions that have not been reduced to short eligibility statements here. Read the complete linked notice for those passages, including any alternatives, exceptions or restrictions. The concise facts above should not be treated as the full wording of every condition.

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Principal RFIC Design Engineer vacancy is not an offer for reference REF33119K; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Western Digital

Applications follow the official employer page linked below. The source includes these application-specific points:

Open the official Western Digital posting below and match the title and reference REF33119K.

Compare your qualifications and experience with the essential conditions for the San Jose, CA, United States position, then read the preferred criteria separately.

Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.

Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.

• Accommodation requests: jobs.accommodations@wdc.com

Preparing a relevant example

Choose an engineering example that matches the project stage and discipline in this vacancy. Explain the problem, your own responsibility, the deliverable and the checks or reviews used. Calculations, drawings, test work, site work and coordination can provide different kinds of evidence.

Relevant skills

• communication