Renesas Electronics: Senior Digital Engineer — Chandler, Arizona, United States

About Renesas Electronics

Renesas Electronics develops semiconductors for automotive, industrial, infrastructure and connected-device applications. Its employer description identifies microcontrollers, system-on-chip devices, analogue components and power products within its portfolio. These components form part of electronic systems made by other manufacturers. Renesas also describes combining complementary products into solutions for customers, connecting individual chips with the needs of an end application. Its business therefore involves both semiconductor technology and how that technology is used in wider electronic products.

The position and its setting

Renesas Electronics lists Senior Digital Engineer in Chandler, Arizona, United States, under reference 20034240_2026-10-20. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

• Employment type: Full-time
• Employer listing date: 22 October 2026
• Brands: Renesas Electronics

Responsibilities and work described

• Renesas Electronics is seeking a skilled and motivated Senior Digital Design Engineer to join our growing hardware development team in Chandler, AZ
• In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications
• Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes
• Support: full product lifecycle from concept to mass-production; communicating closely with wider organization through the various stages of silicon development
• Work: closely with Analog and Verification engineers to deliver high-quality silicon solutions
• Quality / delivery: digital development process is state-of-art and achieves budget, schedule, and project deliverable goals
• Design: digital RTL that meets timing, area, power and any adhering standards specifications
• Integration: design at the top level and running block & top-level simulations
• Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF
• Work: closely with P&R team to generate a layout that meets timing, area, and power requirements
• Support: DFT strategy and implementation, and review test case development
• Support: top level test-bench debug, and running RTL & gate level simulations
• Work: with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification
• Support: analog team to develop AMS, SystemVerilog or Verilog-real behavioral models
• Development: detailed block & chip level design documents and collateral
• Holding and participating in key design reviews and completion of various checklists

Essential requirements and candidate background

• >5 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management
• Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline
• Fluency: Verilog / SystemVerilog RTL for digital CMOS circuit design
• Understanding: ASIC design methodology
• Understanding: Lint, CDC & RDC tools
• Understanding: block-level & chip-level verification techniques
• & ability to debug both RTL & gate-level simulations
• Mandatory competence in written and verbal English
• Willingness to travel domestically or internationally on short notice
• Work independently and collaboratively

Experience and professional background

• Preferred: experience with industry-standard protocols such as AMBA or I2C

Preferred experience and additional strengths

• Preferred: experience with mixed-signal design methodologies
• Preferred: experience developing design constraints and hand-off to P&R
• Preferred: experience with STA and timing closure
• Preferred: experience with low-power design techniques, including clock and power gating (UPF)
• Preferred: experience with power analysis and optimization
• Preferred: experience with advanced verification methodologies (UVM)

Location, schedule and contract conditions

For this overseas or regional listing, confirm work authorisation and any location restrictions with the employer. The location does not establish visa sponsorship or permission to work remotely from India.

• Work arrangement: On-site
• Advertised location: Chandler, Arizona, United States

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Senior Digital Engineer vacancy is not an offer for reference 20034240_2026-10-20; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Renesas Electronics

Applications follow the official employer page linked below.

Open the official Renesas Electronics posting below and match the title and reference 20034240_2026-10-20.

Compare your qualifications and experience with the essential conditions for the Chandler, Arizona, United States position, then read the preferred criteria separately.

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Practical preparation: electrical engineering

For electrical-engineering work, describe the system, the project stage and the work you performed. Design, testing, installation, maintenance and commissioning can call for different evidence.

Relevant skills

• electrical engineering